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1 ltc1274/ltc1277 12-bit, 10mw, 100ksps adcs with 1 a shutdown u a o pp l ic at i ty p i ca l s f ea t u re d u escriptio the ltc 1274/ltc1277 are 8 s sampling 12-bit a/d converters which draw only 2ma (typ) from single 5v or 5v supplies. these easy-to-use devices come complete with a 2 s sample-and-hold, a precision reference and an internally trimmed clock. unipolar and bipolar conversion modes add to the flexibility of the adcs. two power-down modes are available in the ltc1277. in nap mode, the ltc1277 draws only 180 a and the instant wake-up from nap mode allows the ltc1277 to be pow- ered down even during brief inactive periods. in sleep mode only 1 a will be drawn. a refrdy signal is used to show the adc is ready to sample after waking up from sleep mode. the ltc1274 also provides the sleep mode and refrdy signal. the a/d converters convert 0v to 4.096v unipolar inputs from a single 5v supply or 2.048v bipolar inputs from 5v supplies. the ltc1274 has a single-ended input and a 12-bit parallel data format. the ltc1277 offers a differential input and a 2-byte read format. the bipolar mode is formatted as 2? complement for the ltc1274 and offset binary for the ltc1277. low power dissipation: 10mw sample rate: 100ksps samples inputs beyond nyquist, 72db s/(n + d) and 82db thd at f in = 100khz single supply 5v or 5v operation power shutdown to 1 a in sleep mode 180 a nap mode (ltc1277) with instant wake-up internal reference can be overdriven internal synchronized clock 0v to 4.096v or 2.048v input ranges (1mv/lsb) 24-lead so package , ltc and lt are registered trademarks of linear technology corporation. supply current vs sample rate with sleep and nap modes sample rate (hz) supply current ( a) 10000 1000 100 10 1 0.1 1k 100k ltc1274/77 ?ta02 10 1 10k 100 without sleep or nap nap = 5v (sleep mode) nap = refrdy (sleep mode) nap mode c ref = 4.7 f u s a o pp l ic at i battery-powered portable systems high speed data acquisition for pcs digital signal processing multiplexed data acquisition systems audio and telecom processing spectrum analysis 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 a in + a in v ref agnd refrdy sleep nap d7 d6 d5 d4 dgnd v dd v ss busy cs rd convst hben v logic d0/8 d1/9 d2/10 d3/11 ltc1277 0.1 f + 10 f analog differential inputs (0v to 4.096v) 2.42v v ref output 10 f 0.1 f 5v 8-bit parallel bus p control lines optional 3v supply to interface with 3v processor ltc1274/77 ?ta01 + single 5v supply, 10mw, 100khz, 12-bit adc
2 ltc1274/ltc1277 (notes 1, 2) supply voltage (v dd ) ................................................ 7v negative supply voltage (v ss ) bipolar operation only .......................... 6v to gnd total supply voltage (v dd to v ss ) bipolar operation only ....................................... 12v analog input voltage (note 3) unipolar operation ................... ?0.3v to v dd + 0.3v bipolar operation............... v ss ?0.3v to v dd + 0.3v digital input voltage (note 4) unipolar operation .............................. ?0.3v to 12v bipolar operation.......................... v ss ?0.3v to 12v a u g w a w u w a r b s o lu t exi t i s wu u package / o rder i for atio order part number ltc1274csw ltc1274isw order part number ltc1277csw ltc1277isw digital output voltage unipolar operation ................... 0.3v to v dd + 0.3v bipolar operation...................... 0.3v to v dd + 0.3v power dissipation ............................................. 500mw operating temperature range commercial ............................................ 0 c to 70 c industrial ........................................... 40 c to 85 c storage temperature range ................ 65 c to 150 c lead temperature (soldering, 10 sec)................. 300 c t jmax = 110 c, ja = 130 c/w 1 2 3 4 5 6 7 8 9 10 11 12 top view 24 23 22 21 20 19 18 17 16 15 14 13 a in v ref agnd d11 (msb) d10 d9 d8 d7 d6 d5 d4 dgnd v dd v ss busy cs rd convst sleep refrdy d0 d1 d2 d3 sw package 24-lead plastic so wide t jmax = 110 c, ja = 130 c/w 1 2 3 4 5 6 7 8 9 10 11 12 top view 24 23 22 21 20 19 18 17 16 15 14 13 a in + a in v ref agnd refrdy sleep nap d7 d6 d5 d4 dgnd v dd v ss busy cs rd convst hben v logic d0/8 d1/9 d2/10 d3/11 (d11 = msb) sw package 24-lead plastic so wide consult factory for military grade parts. parameter conditions min typ max units resolution (no missing codes) 12 bits integral linearity error (note 7) 1 lsb differential linearity error 1 lsb unipolar offset error 6 lsb 8 lsb bipolar offset error (note 8) 8 lsb 10 lsb gain error 20 lsb gain error tempco i out(ref) = 0 10 45 ppm/ c cc hara terist ics co u verter with internal reference (notes 5, 6)
3 ltc1274/ltc1277 (note 5) symbol parameter conditions min typ max units v in analog input range (note 10) 4.75v v dd 5.25v (unipolar) 0 to 4.096 v 4.75v v dd 5.25v, 5.25v v ss 2.45v (bipolar) 2.048 v i in analog input leakage current cs = high 1 a c in analog input capacitance between conversions (sample mode) 45 pf during conversions (hold mode) 5 pf put u i a a u log accuracy ic dy u w a (notes 5, 9) symbol parameter conditions min typ max units s/(n + d) signal-to-noise 50khz input signal 73 db plus distortion ratio 100khz input signal 70 72.5 db thd total harmonic distortion 50khz input signal 84 db up to 5th harmonic 100khz input signal ?2 76 db peak harmonic or 50khz input signal 84 db spurious noise 100khz input signal ?2 76 db imd intermodulation distortion fa = 96.95khz, fb = 97.68khz 2nd order terms 78 db 3rd order terms 81 db full power bandwidth 2 mhz full linear bandwidth 350 khz [s/(n + d) 68db] i ter al refere ce characteristics u uu (note 5) parameter conditions min typ max units v ref output voltage i out = 0 2.400 2.420 2.440 v v ref output tempco i out = 0 10 45 ppm/ c v ref line regulation 4.75v v dd 5.25v 0.01 lsb/v 5.25v v ss 4.75v 0.01 lsb/v v ref load regulation 5ma i out 70 a 2 lsb/ma (note 5) symbol parameter conditions min typ max units v ih high level input voltage v dd = 5.25v 2.4 v v il low level input voltage v dd = 4.75v 0.8 v i in digital input current v in = 0v to v dd 10 a c in digital input capacitance 5pf v oh high level output voltage, all logic outputs v dd = 4.75v i o = 10 a 4.70 v i o = 200 a 4.0 v v logic = 2.7v (ltc1277) i o = 10 a 2.65 v i o = 200 a 2.60 v v ol low level output voltage, v dd = 4.75v all logic outputs i o = 160 a 0.05 v i o = 1.6ma 0.10 0.4 v v logic =2.7v (ltc1277) i o = 160 a 0.05 v i o = 1.6ma 0.10 v digital i puts a d digital outputs u u
4 ltc1274/ltc1277 symbol parameter conditions min typ max units i oz high-z output leakage d11 to d0/8 v out = 0v to v dd , cs high 10 a c oz high-z output capacitance d11 to d0/8 cs high (note 10) 15 pf i source output source current v out = 0v 10 ma i sink output sink current v out = v dd 10 ma (note 5) digital i puts a d digital outputs u u (note 5) power require e ts w u symbol parameter conditions min typ max units v dd positive supply voltage (notes 11, 12) unipolar and bipolar mode 4.75 5.25 v v logic logic supply (notes 11,12) unipolar and bipolar mode (ltc1277) 2.7 to 5.25 v v ss negative supply voltage (note 11) bipolar mode only 2.45 5.25 v i dd positive supply current f sample = 100ksps 24 ma nap = 0v (ltc1277 only) 180 320 a sleep = 0v 0.3 5 a i ss negative supply current f sample = 100ksps, bipolar mode only 40 70 a sleep = 0v 0.3 5 a p diss power dissipation f sample = 100ksps 10 20 mw nap = 0v (ltc1277 only) 0.9 1.8 mw sleep = 0v (unipolar/bipolar) 25/50 w (note 5) see figures 13 to 17. ti i g characteristics w u symbol parameter conditions min typ max units f sample(max) maximum sampling frequency (note 11) 100 ksps t conv conversion time 68 s t acq acquisition time 0.35 2 s t 1 cs to rd setup time (note 10) 0ns t 2 cs to convst setup time (note 10) 30 ns t 3 nap to convst wake-up time (ltc1277 only) (note 11) 620 ns t 4 convst low time (note 13) 40 ns t 5 convst to busy delay c l = 100pf 70 150 ns t 6 data ready before busy c l = 100pf 20 65 ns t 7 delay between conversions (note 11) 0.35 2 s t 8 wait time rd after busy (note 10) ?0 ns t 9 data access time after rd c l = 20pf (note 10) 50 110 ns 140 ns c l = 100pf 65 125 ns 170 ns t 10 bus relinquish time c l = 100pf 20 60 90 ns 20 100 ns t 11 rd low time (note 10) t 9 ns t 12 convst high time (notes 10, 13) 40 ns t 13 aperture delay of sample-and-hold 35 ns t 14 sleep to refrdy wake-up time 10 f bypass at v ref pin 4.2 ms 4.7 f bypass at v ref pin 3.3 ms t 15 hben to high byte data valid c l = 100pf (ltc1277 only) 35 100 ns
5 ltc1274/ltc1277 (note 5) see figures 13 to 17. ti i g characteristics w u symbol parameter conditions min typ max units t 16 hben to low byte data valid c l = 100pf (ltc1277 only) 45 100 ns t 17 hben to rd setup time (note 10) (ltc1277 only) 10 ns t 18 rd to hben setup time (note 10) (ltc1277 only) 10 ns the denotes specifications which apply over the full operating temperature range; all other limits and typicals t a = 25 c. note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: all voltage values are with respect to ground with dgnd and agnd wired together and v logic is tied to v dd in ltc1277 (unless otherwise noted). note 3: when these pin voltages are taken below v ss (ground for unipolar mode) or above v dd , they will be clamped by internal diodes. this product can handle input currents greater than 60ma below v ss (ground for unipolar mode) or above v dd without latch-up. note 4: when these pin voltages are taken below v ss (ground for unipolar mode), they will be clamped by internal diodes. this product can handle input currents greater than 60ma below v ss (ground for unipolar mode) without latch-up. these pins are not clamped to v dd . note 5: v dd = 5v (v ss = 5v for bipolar mode), v logic = v dd (ltc1277), f sample = 100ksps, t r = t f = 5ns unless otherwise specified. note 6: linearity, offset and full-scale specifications apply for unipolar and bipolar modes. note 7: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 8: for ltc1274, bipolar offset is the offset voltage measured from 0.5lsb when the output code flickers between 0000 0000 0000 and 1111 1111 1111. for ltc1277, bipolar offset voltage is measured from 0.5lsb when the output code flickers between 0111 1111 1111 and 1000 0000 0000. note 9: the ac tests apply to bipolar mode only and the s/(n + d) is 71db (typ) for unipolar mode at 100khz input frequency. note 10: guaranteed by design, not subject to test. note 11: recommended operating conditions. note 12: a in must not exceed v dd or fall below v ss by more than 50mv to specified accuracy. note 13: the falling convst edge starts a conversion. if convst returns high at a bit decision point during the conversion it can create small errors. for best performance ensure that convst returns high either within 400ns after conversion start (i.e., before the first bit decision) or after busy rises (i.e., after the last bit test). see timing diagrams modes 1a and 1b (figures 13, 14). typical perfor m a n ce characteristics u w integral nonlinearity vs output code output code 0 1.00 integral nonlinearity error (lsb) 0.50 0 0.50 1.00 512 1024 1536 2048 lt1274/77 ?tpc01 2560 3072 3584 4096 f sample = 100khz input frequency (hz) 10k effective number of bits (enobs) 12 11 10 9 8 7 6 5 4 3 2 1 0 s/(n + d)(db) 74 68 62 56 50 100k 1m 2m ltc1274/77 ?tpc03 f sample = 100khz nyquist frequency output code 0 1.00 differential nonlinearity error (lsb) 0.50 0 0.50 1.00 512 1024 1536 2048 lt1274/77 ?tpc02 2560 3072 3584 4096 f sample = 100khz differential nonlinearity vs output code enobs and s/(n + d) vs input frequency
6 ltc1274/ltc1277 typical perfor m a n ce characteristics u w signal-to-noise ratio (without harmonics) vs input frequency input frequency (hz) 10k signal/(noise + distortion)(db) 100k 2m 1m ltc1274/77 ?tpc04 80 70 60 50 40 30 20 10 0 v in = 60db v in = 20db v in = 0db f sample = 100khz input frequency (hz) 10k signal-to-noise ratio (db) 100k 2m 1m ltc1274/77 ?tpc05 80 70 60 50 40 30 20 10 0 f sample = 100khz distortion vs input frequency thd input frequency (hz) 10k distortion (db) 0 ?0 ?0 ?0 ?0 100 120 100k 1m 2m ltc1274/77 ?tpc06 3rd harmonic 2nd harmonic f sample = 100khz input frequency (hz) 10k spurious-free dynamic range (db) 100k 2m 1m ltc1274/77 ?tpc07 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 100 f sample = 100khz spurious-free dynamic range vs input frequency intermodulation distortion plot s/(n + d) vs input frequency and amplitude frequency (khz) 0 amplitude (db) 0 ?0 ?0 ?0 ?0 100 120 10 20 30 40 ltc1274/77 ?tpc08 50 fb ?fa 2fb ?fa 2fa ?fb 2fa 2fb 3fb fa + 2fb 3fa 2fa ?fb f sample = 100khz fa = 9.54khz fb = 9.79khz fb ?fa source resistance ( ? ) 10 acquisition time ( s) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 100 1k 10k ltc1274/75 ?tpc10 t a = 25 c acquistion time vs source impedance intermodulation distortion plot frequency (hz) 0 amplitude (db) 0 ?0 ?0 ?0 ?0 100 120 10k 20k 30k 40k ltc1274/77 ?tpc09 50k 2fb ?fa fb fa fb ?fa 2fb 2fa ?fb 2fa 3fb 2fb + fa 2fa + fb fa + fb 3fa f sample = 100khz fa = 96.948khz fb = 97.681khz
7 ltc1274/ltc1277 typical perfor m a n ce characteristics u w reference voltage vs load current load current (ma) ? reference voltage (v) 2.435 2.430 2.425 2.420 2.415 2.410 2.405 ? ? lt1274/77 ?tpc13 ? ? ? 0 1 supply current vs temperature temperature ( c) ?5 supply current (ma) 3.0 2.5 2.0 1.5 1.0 0.5 0 25 75 lt1274/77 ?tpc11 ?5 0 50 100 125 f sample = 100khz power supply feedthrough vs ripple frequency ripple frequency (khz) 1 amplitude of power supply feedthrough (db) 10 100 1000 ltc1274/77 ?tpc12 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 f sample = 100khz av dd (v ripple = 1mv) v ss (v ripple = 10mv) dgnd (v ripple = 0.1v) supply current vs sample rate with sleep and nap modes sample rate (hz) supply current ( a) 10000 1000 100 10 1 0.1 1k 100k ltc1274/77 ?tpc15 10 1 10k 100 without sleep or nap nap = 5v (sleep mode) nap = refrdy (sleep mode) nap mode c ref = 4.7 f wake-up time vs c ref (sleep mode) supply current vs supply voltage c ref ( f) 0 wake-up time (ms) 10 9 8 7 6 5 4 3 2 1 0 40 ltc1274/77 ?tpc16 10 515253545 20 30 50 t a = 25 c supply voltage (v) 0 supply current (ma) 3.0 2.5 2.0 1.5 1.0 0.5 0 1 234 ltc1274/77 ?tpc14 56 f sample = 100khz pi fu ctio s uu u ltc1274 a in (pin 1): analog input. 0v to 4.096v, unipolar (v ss = 0v) or 2.048v, bipolar (v ss = 5v). v ref (pin 2): 2.42v reference output. bypass to agnd (10 f tantalum in parallel with 0.1 f ceramic). v ref can be overdriven positive with an external reference voltage. agnd (pin 3): analog ground. d11 to d4 (pins 4 to 11): three-state data outputs. d11 is the most significant bit. dgnd (pin 12): digital ground. d3 to d0 (pins 13 to 16): three-state data outputs. refrdy (pin 17): reference ready signal. it goes high when the reference has settled after sleep indicating that the adc is ready to sample. sleep (pin 18): sleep mode input. tie this pin to low to put the adc in sleep mode and save power (refrdy will go low). the device will draw 1 a in this mode. convst (pin 19): conversion start signal. this active low signal starts a conversion on its falling edge (to recognize convst, cs has to be low.)
8 ltc1274/ltc1277 pi fu ctio s uu u *the ltc1277 bipolar mode is in offset binary. rd (pin 20): read input. this enables the output drivers when cs is low. cs (pin 21): the chip select input must be low for the adc to recognize convst and rd inputs. busy (pin 21): the busy output shows the converter status. it is low when a conversion is in progress. the rising busy edge can be used to latch the conversion result. v ss (pin 23): negative 5v supply. negative 5v will select bipolar operation. bypass to agnd with 0.1 f ceramic. tie this pin to analog ground to select unipolar operation. v dd (pin 24): positive 5v supply. bypass to agnd (10 f tantalum in parallel with 0.1 f ceramic). ltc1277 a in + (pin 1): positive analog input. (a in + ?a in ) = 0v to 4.096v, unipolar (v ss = 0v) or 2.048v, bipolar (v ss = 5v). a in (pin 2): negative analog input. this pin needs to be free of noise during conversion. for single-ended inputs tie a in to analog ground. v ref (pin 3): 2.42v reference output. bypass to agnd (10 f tantalum in parallel with 0.1 f ceramic). v ref can be overdriven positive with an external reference voltage. agnd (pin 4): analog ground. refrdy (pin 5): reference ready signal. it goes high when the reference has settled after sleep indicating that the adc is ready to sample. sleep (pin 6): sleep mode input. tie this pin to low to put the adc in sleep mode and save power (refrdy will go low). the device will draw 1 a in this mode. nap (pin 7): nap mode input. pulling this pin low will shut down all currents in the adc except the reference. in this mode the adc draws 180 a. wake-up from nap mode is about 620ns. d7 to d4* (pins 8 to 11): three-state data outputs. dgnd (pin 12): digital ground. d3/11 to d0/8* (pins 13 to 16): three-state data outputs. d11 is the most significant bit. v logic (pin 17): 5v or 3v digital power supply. this pin allows a 5v or 3v logic interface with the processor. all logic outputs (data bits, busy and refrdy) will swing between 0v and v logic . hben (pin 18): high byte enable input. the four most significant bits will appear at pins 13 to 16 when this pin is high. the ltc1277 uses straight binary for unipolar mode and offset binary for bipolar mode. convst (pin 19): conversion start signal. this active low signal starts a conversion on its falling edge (to recognize convst, cs has to be low). rd (pin 20): read input. this enables the output drivers when cs is low. cs (pin 21): the chip select input must be low for the adc to recognize convst and rd inputs. busy (pin 22): the busy output shows the converter status. it is low when a conversion is in progress. v ss (pin 23): negative 5v supply. negative 5v will select bipolar operation. bypass to agnd with 0.1 f ceramic. tie this pin to analog ground to select unipolar operation. v dd (pin 24): 5v positive supply. bypass to agnd (10 f tantalum in parallel with 0.1 f ceramic). table 1. ltc1277 two-byte read data bus status data outputs d7 d6 d5 d4 d3/11 d2/10 d1/9 d0/8 low byte db7 db6 db5 db4 db3 db2 db1 db0 high byte low low low low db11 db10 db9 db8
9 ltc1274/ltc1277 block diagra s w ltc1274 12-bit capacitive dac comparator c sample d11 d0 busy control logic cs convst rd internal clock sleep zeroing switches v ss (0v for unipolar mode or ?v for bipolar mode) v dd a in v ref refrdy agnd dgnd 12 ltc1274 ?bd successive approximation register output latches 2.42v ref ltc1277 12-bit capacitive dac comparator c sample d7 d1/9 d0/8 busy v logic 3v or 5v control logic cs convst rd internal clock sleep hben nap zeroing switches v ss (0v for unipolar mode or ?v for bipolar mode) v dd a in a in + v ref refrdy agnd dgnd 12 ltc1277 ?bd successive approximation register output latches 2.42v ref test circuits load circuits for output float delay load circuits for access timing 3k c l dbn dgnd a) high-z to v oh (t 9 ) and v ol to v oh (t 6 ) c l dbn 3k 5v b) high-z to v ol (t 9 ) and v oh to v ol (t 6 ) dgnd 1274/77 ?tc01 3k 10pf dbn dgnd a) v oh to high-z 10pf dbn 3k 5v b) v ol to high-z dgnd 1274/77 ?tc02
10 ltc1274/ltc1277 ti i g diagra s w w u cs to rd setup timing cs to convst setup timing t 1 cs rd ltc1274/77 ?td01 t 2 cs convst ltc1274/77 ?td02 nap to convst wake-up timing (ltc1277) sleep to refrdy wake-up timing t 3 nap convst ltc1274/77 ?td03 t 14 sleep refrdy ltc1274/77 ?td04 applicatio n s i n for m atio n wu u u conversion details the ltc1274/ltc1277 use a successive approximation algorithm and an internal sample-and-hold circuit to con- vert an analog signal to a 12-bit parallel output. the adcs are complete with a precision reference and an internal clock. the control logic provides easy interface to micro- processors and dsps. (please refer to the digital interface section for the data format.) conversion start is controlled by the cs and convst inputs. at the start of conversion the successive approxi- mation register (sar) is reset. once a conversion cycle has begun it cannot be restarted. during conversion, the internal 12-bit capacitive dac out- put is sequenced by the sar from the most significant bit (msb) to the least significant bit (lsb). referring to figure 1, the a in (ltc1274) or a in + (ltc1277) input con- nects to the sample-and-hold capacitor during the acquire phase, and the comparator offset is nulled by the feedback switch. in this acquire phase, a minimum delay of 2 s will provide enough time for the sample-and-hold capacitor to acquire the analog signal. during the convert phase, the comparator feedback switch opens, putting the comparator into the compare mode. the input switch connects c sample to ground (ltc1274) or a in (ltc1277), injecting the analog input charge onto the summing junction. this input charge is successively compared with the binary-weighted charges supplied by the capacitive dac. bit decisions are made by the high speed comparator. at the end of a conversion, the dac output balances the a in (ltc1274) or a in + ?a in (ltc1277) input charge. the sar contents (a 12- bit data word) which represent the a in (ltc1274) or a in + ?a in (ltc1277) are loaded into the 12-bit output latches. v dac 1274 ?f01 + c dac dac sample hold c sample s a r 12-bit latch compar- ator sample si a in figure 1. ltc1274 a in input dynamic performance the ltc1274/ltc1277 have excellent high speed sam- pling capability. fft (fast fourier transform) test tech- niques are used to test the adcs?frequency response, distortion and noise at the rated throughput. by applying a low distortion sine wave and analyzing the digital output
11 ltc1274/ltc1277 applicatio n s i n for m atio n wu u u using an fft algorithm, the adcs?spectral content can be examined for frequencies outside the fundamental. figures 2a and 2b show typical ltc1274 fft plots. signal-to-noise ratio the signal-to-noise plus distortion ratio [s/(n + d)] is the ratio between the rms amplitude of the fundamental input frequency to the rms amplitude of all other fre- quency components at the a/d output. the output is band limited to frequencies above dc and below half the sam- pling frequency. figure 2a shows a typical spectral con tent with a 100khz sampling rate and a 48.85khz input. the dynamic performance is excellent for input frequencies well beyond nyquist as shown in figure 2b and figure 3. input frequency (khz) 0 amplitude (db) 0 ?0 ?0 ?0 ?0 100 120 10 20 30 40 ltc1274/77 ?f02a 50 f sample = 100khz f in = 48.85khz figure 2a. ltc1274 nonaveraged, 4096 point fft plot with 50khz input frequency input frequency (khz) 0 amplitude (db) 0 ?0 ?0 ?0 ?0 100 120 10 20 30 40 ltc1274/77 ?f02b 50 f sample = 100khz f in = 97.68khz figure 2b. ltc1274 nonaveraged, 4096 point fft plot with 100khz input frequency effective number of bits the effective number of bits (enobs) is a measurement of the resolution of an adc and is directly related to the s/(n + d) by the equation: n = [s/(n + d) ?1.76]/6.02 where n is the effective number of bits of resolution and s/(n + d) is expressed in db. at the maximum sampling rate of 100khz, the ltc1274/ltc1277 maintain very good enobs over 300khz. refer to figure 3. total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of all harmonics of the input signal to the fundamen- tal itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency. thd is expressed as: thd = 20log v 2 2 + v 3 2 + v 4 2 ... + v n 2 v 1 where v 1 is the rms amplitude of the fundamental fre- quency and v 2 through v n are the amplitudes of the second through nth harmonics. thd versus input fre- input frequency (hz) 10k effective number of bits (enobs) 12 11 10 9 8 7 6 5 4 3 2 1 0 s/(n + d)(db) 74 68 62 56 50 100k 1m 2m ltc1274/77 ?f03 f sample = 100khz nyquist frequency figure 3. enobs and s/(n + d) vs input frequency
12 ltc1274/ltc1277 applicatio n s i n for m atio n wu u u full-power and full-linear bandwidth the full-power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is re- duced by 3db for a full-scale input signal. the full-linear bandwidth is the input frequency at which the s/(n + d) has dropped to 68db (11 effective bits). the ltc1274/ltc1277 have been designed to optimize input bandwidth, allowing adcs to undersample input signals with frequencies above the converter? nyquist frequency. the noise floor stays very low at high frequencies; s/(n + d) becomes dominated by distortion at frequencies far beyond nyquist. driving the analog input the analog input of the ltc1274/ltc1277 is easy to drive. it draws only one small current spike while charg- ing the sample-and-hold capacitor at the end of conver- sion. during conversion the analog input draws only a small leakage current. the only requirement is that the amplifier driving the analog input must settle after the small current spike before the next conversion starts. any op amp that settles in 2 s to small current transients will allow maximum speed operation. if slower op amps are used, more settling time can be provided by increasing the time between conversions. suitable devices capable of driving the adc a in input include the lt 1006, lt1007, lt1220, lt1223 and lt1224 op amps. quency is shown in figure 4. the adcs have good distor- tion performance up to the nyquist frequency and beyond. intermodulation distortion if the adc input signal consists of more than one spectral component, the adc transfer function nonlinearity can pro- duce intermodulation distortion (imd) in addition to thd. imd is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. if two pure sine waves of frequencies fa and fb are applied to the adc input, nonlinearities in the adc transfer func- tion can create distortion products at sum and difference frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc. for example, the 2nd order imd terms include (fa + fb) and (fa ?fb) while the 3rd order imd terms include (2fa + fb), (2fa ?fb), (fa + 2fb) and (fa ?2fb). if the two input sine waves are equal in magnitude, the value (in decibels) of the 2nd order imd products can be expressed by the following formula: imd (fa ?fb) = 20log amplitude at (fa ?fb) amplitude at fa figure 5 shows the imd performance at a 97khz input. peak harmonic or spurious noise the peak harmonic or spurious noise is the largest spec- tral component excluding the input signal and dc. this value is expressed in decibels relative to the rms value of a full scale input signal. figure 4. distortion vs input frequency figure 5. intermodulation distortion frequency (hz) 0 amplitude (db) 0 ?0 ?0 ?0 ?0 100 120 10k 20k 30k 40k ltc1274/77 ?f05 50k 2fb ?fa fb fa fb ?fa 2fb 2fa ?fb 2fa 3fb 2fb + fa 2fa + fb fa + fb 3fa f sample = 100khz fa = 96.948khz fb = 97.681khz thd input frequency (hz) 10k distortion (db) 0 ?0 ?0 ?0 ?0 100 120 100k 1m 2m ltc1274/77 ?f04 3rd harmonic 2nd harmonic f sample = 100khz
13 ltc1274/ltc1277 u s a o pp l ic at i wu u i for atio 3v to keep the input span within the 5v supply in unipolar mode. in bipolar mode the reference should be driven to no more than 5v, the positive supply voltage of the chip. figure 6 shows an lt1006 op amp driving the reference pin. in unipolar mode, the reference can be driven up to 2.95v at which point it will provide a 0v to 5v input span. for the bipolar mode, the reference can be driven up to 5v at which point it will provide a 4.23v input span. figure 7 shows a typical reference, the lt1019a-2.5 connected to the ltc1274. this will provide an improved drift (equal to the maximum 5ppm/ c of the lt1019a-2.5) and a 2.115v (bipolar) or 4.231v (unipolar) full scale. board layout and bypassing wire wrap boards are not recommended for high resolu- tion or high speed a/d converters. to obtain the best performance from the ltc1274/ltc1277, a printed cir- cuit board is required. layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital track alongside an analog signal track or underneath the adc. the analog input should be screened by agnd. high quality tantalum and ceramic bypass capacitors should be used at the v dd and v ref pins as shown in ltc1277 a in + /a in input settling the input capacitor for the ltc1277 is switched onto the a in + input during the sample phase. the voltage on the a in + input must settle completely within the sample period. at the end of the sample phase the input capacitor switches to the a in input and the conversion starts. during the conversion the a in + input voltage is effec- tively ?eld?by the sample-and-hold and will not affect the conversion result. it is critical that the a in input voltage be free of noise and settles completely during the conversion. internal reference the adcs have an on-chip, temperature compensated, curvature corrected bandgap reference which is factory trimmed to 2.42v. it is internally connected to the dac and is available at pin 2 (ltc1274) or pin 3 (ltc1277) to provide up to 1ma current to an external load. for minimum code transition noise the reference output should be decoupled with a capacitor to filter wideband noise from the reference (10 f tantalum in parallel with a 0.1 f ceramic). the v ref pin can be driven with a dac or other means to provide input span adjustment. the v ref pin must be driven to at least 2.45v to prevent conflict with the internal reference. the reference should be driven to no more than figure 6. driving the v ref with the lt1006 op amp v ref(out) 2.45v 3 ? input range: 0.846v ref(out) in bipolar mode 0 to 1.69v ref(out) in unipolar mode 5v + lt1006 ltc1274 a in agnd v ref 10 f ltc1274/77 ?f06 figure 7. supplying a 2.5v reference voltage to the ltc1274 with the lt1019a-2.5 3 ? input range: 2.115v ( 0.846 v ref ) in bipolar and 0v to 4.231v (1.69v ref(out) ) in unipolar mode ltc1274 a in agnd v ref 10 f ltc1274/77 ?f07 lt1019a-2.5 v in gnd v out 5v 5v
14 ltc1274/ltc1277 u s a o pp l ic at i wu u i for atio figure 8. for bipolar mode, a 0.1 f ceramic provides adequate bypassing for the v ss pin. the capacitors must be located as close to the pins as possible. the traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. input signal leads to a in and signal return leads from agnd (pin 3 for ltc1274, pin 4 for ltc1277) should be kept as short as possible to minimize input noise cou- pling. in applications where this is not possible a shielded cable between source and adc is recommended. also, since any potential difference in grounds between the signal source and the adc appears as an error voltage in series with the input signal, attention should be paid to reducing the ground circuit impedances as much as possible. a single point analog ground separate from the logic system ground should be established with an analog ground plane at agnd or as close as possible to the adc. dgnd (pin 12) and all other analog grounds should be connected to this single analog ground point. no other digital grounds should be connected to this analog ground point. low impedance analog and digital power supply common returns are essential to low noise operation of the adc and the foil width for these tracks should be as wide as possible. in applications where the adc data outputs and control signals are connected to a continu- ously active microprocessor bus, it is possible to get errors in conversion results. these errors are due to feedthrough from the microprocessor to the successive approximation comparator. the problem can be elimi- nated by forcing the microprocessor into a wait state during conversion or by using three-state buffers to isolate the adc data bus. figure 9 is a typical application circuit for the ltc1274. figure 8. power supply grounding practice figure 9. ltc1274 typical circuit 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 a in v ref agnd d11 (msb) d10 d9 d8 d7 d6 d5 d4 dgnd v dd v ss busy cs rd convst sleep refrdy d0 d1 d2 d3 ltc1274 0.1 f + 10 f analog input (0v to 4.095v) 2.42v v ref output 10 f 0.1 f 5v 12-bit parallel bus p control lines conversion start input sleep mode input reference ready signal ltc1274/77 ?f09 + ltc1274/77 ?f08 a in agnd v ref av dd dv dd dgnd ltc1274 digital system 0.1 f + analog ground plane ground connection to digital circuitry analog input circuitry 3 2 24 17 12 1 0.1 f 10 f 10 f
15 ltc1274/ltc1277 u s a o pp l ic at i wu u i for atio digital interface the adcs are designed to interface with microproces- sors as a memory mapped device. the cs and rd control inputs are common to all peripheral memory interfacing. a separate convst is used to initiate a conversion. figures 10a to 10c are the input/output characteristics of the adcs. the code transitions occur midway between successive integer lsb values (i.e., 0.5lsb, 1.5lsb, 2.5lsb?s ?1.5lsv). the output code is scaled such that 1.0lsb = fs/4096 = 4.096v/4096 = 1.0mv. unipolar offset and full-scale error adjustments in applications where absolute accuracy is important, then offset and full-scale errors can be adjusted to zero. offset error must be adjusted before full-scale error. figure 11a shows the extra components required for full-scale error adjustment. if both offset and full-scale adjustments are needed, the circuit in figure 11b can be used. for zero offset error, apply 0.50mv (i.e., 0.5lsb) at the input and adjust the offset trim until the ltc1274/ltc1277 output code flickers between 0000 0000 0000 and 0000 0000 0001. for zero full-scale error, apply an analog input of 4.0945v (i.e., fs ?1.5lsb or last code transition) at the input and adjust r5 until the adc output code flickers between 1111 1111 1110 and 1111 1111 1111. bipolar offset and full-scale error adjustments bipolar offset and full-scale errors are adjusted in a similar fashion to the unipolar case. again, bipolar offset must be input voltage (v) 0v output code ? lsb ltc1274/77 ?f10c 111...111 111...110 100...001 100...000 000...000 000...001 011...110 1 lsb bipolar zero 011...111 fs/2 ?1lsb fs/2 1lsb = = = 1mv 4.096v 4096 fs 4096 figure 10c. ltc1277 bipolar transfer characteristics (offset binary) figure 10a. ltc1274/ltc1277 unipolar transfer characteristics figure 10b. ltc1274 bipolar transfer characteristics (2? complement) input voltage (v) 0v output code fs ?1lsb ltc1274/77 f10a 111...111 111...110 111...101 111...100 000...000 000...001 000...010 000...011 1 lsb unipolar zero 1lsb = fs 4096 4.096v 4096 = = 1mv input voltage (v) 0v output code ? lsb ltc1274/77 ?f10b 011...111 011...110 000...001 000...000 100...000 100...001 111...110 1 lsb bipolar zero 111...111 fs/2 ?1lsb fs/2 1lsb = = = 1mv 4.096v 4096 fs 4096
16 ltc1274/ltc1277 u s a o pp l ic at i wu u i for atio ltc1274 ltc1277 a in (ltc1274) a in + (ltc1277) agnd a in (ltc1277) ltc1274/77 f11a r4 100 ? full-scale adjust r3 10k r2 10k r1 50 ? v1 + a1 additional pins omitted for clarity 20lsb trim range ltc1274/77 f11b r2 10k r4 100k r1 10k 10k 5v r9 20 ? analog input 0v to 4.096v r3 100k 5v r8 10k offset adjust r6 400 ? r5 4.3k full-scale adjust r7 100k + ltc1274 ltc1277 a in (ltc1274) a in + (ltc1277) a in (ltc1277) figure 11a. full-scale adjust circuit figure 11b. ltc1274/ltc1277 unipolar offset and full-scale adjust circuit figure 11c. ltc1274/ltc1277 bipolar offset and full-scale adjust circuit adjusted before full-scale error. bipolar offset error ad- justment is achieved by trimming the offset adjust while the input voltage is 0.5lsb below ground. this is done by applying an input voltage of 0.50mv ( 0.5lsb) to the input in figure 11c and adjusting the r8 until the adc? output code flickers between 0000 0000 0000 and 1111 1111 1111 in ltc1274 or between 0111 1111 1111 and 1000 0000 0000 in ltc1277. for full-scale adjustment, an input voltage of 2.0465v (fs ?1.5lsbs) is applied to the input and r5 is adjusted until the output code flickers between 0111 1111 1110 and 0111 1111 1111 in ltc1274 or between 1111 1111 1110 and 1111 1111 1111 in ltc1277. internal clock the a/d converters have an internal clock that eliminates the need of synchronization between the external clock and the cs and rd signals found in other adcs. the internal clock is factory trimmed to achieve a typical conversion time of 6 s. no external adjustments are required and with the maximum acquisition time of 2 s throughput performance of 100ksps is assured. timing and control conversion start and data read operations are controlled by three digital inputs in the ltc1274: cs, convst and rd. for the ltc1277 there are four digital inputs: cs, convst, rd and hben. figure 12 shows the logic structure associated with these inputs for ltc1277. a falling edge on convst will start a conversion after the adc has been selected (i.e., cs is low). once initiated, it cannot be restarted until the conversion is complete. converter status is indicated by the busy output and this is low while conversion is in progress. the high byte enable input (hben) in the ltc1277 is to multiplex the 12 bits of conversion data onto the lower d7 to d0/8 outputs. figures 13 through 17 show several different modes of operation. in modes 1a and 1b (figures 13 and 17) cs and rd are both tied low. the falling edge of convst starts the conversion. the data outputs are always enabled and data can be latched with the busy rising edge. mode 1a shows operation with a narrow logic low convst pulse. mode 1b shows a narrow logic high convst pulse. ltc1274/77 f11c r2 10k r4 100k r1 10k analog input r3 100k 5v r8 20k offset adjust r6 200 ? r5 4.3k full-scale adjust r7 100k + ?v ltc1274 ltc1277 a in (ltc1274) a in + (ltc1277) a in (ltc1277)
17 ltc1274/ltc1277 in slow memory mode the processor applies a logic low to rd (= convst), starting the conversion. busy goes low, forcing the processor into a wait state. the previous conversion result appears on the data outputs. when the conversion is complete, the new conversion results ap- pear on the data outputs; busy goes high releasing the processor; the processor applies a logic high to rd (= convst) and reads the new conversion data. in rom mode the processor applies a logic low to rd (= convst), starting a conversion and reading the previous conversion result. after the conversion is com- plete, the processor can read the new result and initiate another conversion. the narrow logic pulse on convst ensures that convst doesn? return high during the conversion (see note 13 following the timing characteristics table). in mode 2 (figure 15) cs is tied low. the falling edge of convst signal again starts the conversion. data outputs both are in three-state until read by the mpu with the rd signal. mode 2 can be used for operation with a shared mpu databus. in slow memory and rom modes (figures 16 and 17) cs is tied low and convst and rd are tied together. the mpu starts the conversion and reads the output with the rd signal. conversions are started by the mpu or dsp (no external sample clock). data (n ?1) db11 to db0 data (n ?1) db7 to db0 convst busy ltc1274/77 ?f13 t 16 t 15 t 4 t 5 t 6 cs = rd = 0 hben (ltc1277) data n db11 to db0 data n db7 to db0 data n db11 to db8 data n db7 to db0 data (n + 1) db11 to db0 data (n + 1) db7 to db0 ltc1274 data ltc1277 data t 7 t conv (sample n) (sample n + 1) (convst = ) figure 13. mode 1a. convst starts a conversion. data outputs always enabled u s a o pp l ic at i wu u i for atio conversion start (rising edge trigger) 1274/77 ?f12 busy flip flop clear q d active high enable three-state outputs db11....db0 cs rd convst nap sleep figure 12. internal logic for control inputs cs, rd, convst, nap and sleep (ltc1277)
18 ltc1274/ltc1277 u s a o pp l ic at i wu u i for atio figure 15. mode 2. convst starts a conversion. data is read by rd convst busy rd ltc1274/77 ?f15 t 17 t 4 t 5 t 11 t 16 cs = 0 hben (ltc1277) data n db11 to db0 data n db11 to db8 data n db7 to db0 ltc1274 data ltc1277 data t 8 t 9 t conv t 12 (sample n) (sample n + 1) t 10 t 7 figure 14. mode 1b. convst starts a conversion. data outputs always enabled (convst = ) data (n ?1) db11 to db0 convst busy ltc1274/77 ?f14 t 12 t 16 t 5 t 5 cs = rd = 0 hben (ltc1277) data n db11 to db0 data (n ?1) db11 to db8 data (n ?1) db7 to db0 data n db7 to db0 data n db7 to db0 data (n + 1) db7 to db0 data n db11 to db8 data (n ?1) db7 to db0 data (n + 1) db11 to db0 ltc1274 data ltc1277 data t 7 t conv (sample n) t 6 t 15 (sample n + 1)
19 ltc1274/ltc1277 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. u s a o pp l ic at i wu u i for atio the ltc1277 has an additional nap mode. when nap (pin 7) is tied low, all the power is off except the internal reference which is still active and provides 2.42v output voltage to the other circuitry. in this mode the adc draws 0.9mw instead of 10mw (for minimum power, the logic inputs must be within 600mv from the supply rails). the wake-up time from the power shutdown to active state is 620ns. the typical performance graph on the front page of this data sheet shows that the power will be reduced greatly by using the sleep and nap modes. power shutdown the ltc1274/ltc1277 provide shutdown features that will save power when the adc is in inactive periods. both adcs have a sleep mode. to power down the adcs, sleep (pin 18 in ltc1274 or pin 6 in ltc1277) needs to be driver low. when in sleep mode, the ltc1274/ltc1277 will not start a conversion even though the convst goes low. the parts draw 1 a. after release from the sleep mode, the adcs need 3ms (4.7 f bypass capacitor on v ref pin) to wake up and a refrdy signal will go to high to indicate the adc is ready to do conversions. rd = convst busy ltc1274/77 ?f16 t 15 t 18 cs = 0 hben (ltc1277) data n db11 to db0 data n db7 to db0 data (n ?1) db7 to db0 data (n ?1) db11 to db0 data n db11 to db8 ltc1274 data ltc1277 data t 5 t 9 t 6 t 10 t 7 (sample n) data (n + 1) db7 to db0 data n db11 to db0 data (n + 1) db11 to db8 (sample n + 1) data (n + 1) db11 to db0 data n db11 to db0 t conv figure 16. slow memory mode rd = convst busy ltc1274/77 ?f17 t 15 cs = 0 hben (ltc1277) data (n ?1) db11 to db0 data (n ?1) db7 to db0 data (n ?1) db11 to db8 ltc1274 data ltc1277 data t 5 t 18 t 9 t 10 t 7 (sample n) data n db7 to db0 data n db11 to db8 (sample n + 1) data n db11 to db0 t conv figure 17. rom mode timing
20 ltc1274/ltc1277 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 telex : 499-3977 ? linear technology corporation 1995 lt/gp 1195 10k ?printed in usa u s a o pp l ic at i wu u i for atio u package d e sc r i pti o dimensions in inches (millimeters) unless otherwise noted. related parts part number description comments ltc1272 12-bit, 3 s, 250khz sampling a/d converter single 5v, sampling 7572 upgrade ltc1273/75/76 12-bit, 300ksps sampling a/d converters with reference complete with clock, reference ltc1278 12-bit, 500ksps sampling a/d converter with shutdown 70db sinad at nyquist, low power ltc1279 12-bit, 600ksps sampling a/d converter with shutdown 70db sinad at nyquist, low power ltc1282 12-bit, 140ksps sampling a/d converter with reference 3v or 3v adc with reference, clock ltc1409 12-bit, 800ksps sampling a/d converter with shutdown fast, complete low power adc, 80mv ltc1410 12-bit, 1.25msps sampling a/d converter with shutdown fast, complete wideband adc, 160mv in the sleep mode, the comparator of the adc will start consuming power after the rising edge of sleep as shown in figure 18a. if refrdy is tied to nap, the comparator will be powered up after refrdy? rising edge. hence more power will be saved as in figure 18b. refrdy comparator status on off on ltc1274/77 ?f18a sleep 3ms (c ref = 4.7 f) nap = refrdy comparator status on off on ltc1274/77 ?f18b sleep 3ms (c ref = 4.7 f) figure 18a. power saved in sleep mode (nap = high) figure 18b. power saved in sleep mode (nap = refrdy) sw package 24-lead plastic small outline (wide 0.300) (ltc dwg # 05-08-1620) note 1 0.598 ?0.614* (15.190 ?15.600) 22 21 20 19 18 17 16 15 1 23 4 5 6 78 0.394 ?0.419 (10.007 ?10.643) 910 13 14 11 12 23 24 0.037 ?0.045 (0.940 ?1.143) 0.004 ?0.012 (0.102 ?0.305) 0.093 ?0.104 (2.362 ?2.642) 0.050 (1.270) typ 0.014 ?0.019 (0.356 ?0.482) 0 ?8 typ note 1 0.009 ?0.013 (0.229 ?0.330) 0.016 ?0.050 (0.406 ?1.270) 0.291 ?0.299** (7.391 ?7.595) 45 0.010 ?0.029 (0.254 ?0.737) note: 1. pin 1 ident, notch on top and cavities on the bottom of packages are the manufacturing options the part may be supplied with or without any of the options. dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * **

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